The present invention relates to a phase locked loop, and more specifically to a start-up circuit for a phase locked loop.
Recent years have seen advancements in the field of electronic circuits and communication systems. Phase locked loops (PLLs) are an integral part of these circuits and systems. A PLL is used to generate an oscillating signal based on a reference signal. The oscillating signal is used for modulation and demodulation of a message signal in communication systems. The oscillating signal also is used in electronic circuits as a clock signal for synchronous operations within the circuit.
A PLL includes a voltage controlled oscillator (VCO). The VCO requires a trigger voltage signal for initiating the generation of an output signal. The trigger voltage signal is generated by a start-up circuit connected to the PLL.
FIG. 1 is a schematic diagram of a conventional start-up circuit 100 for a PLL. The start-up circuit 100 includes a voltage source 102, a switch 106, a capacitor 108, and a VCO 110. The voltage source 102 is connected to one side of the switch 106. The switch 106 receives a start-up signal 104, generated by an external source, which controls it's switching. The other side the switch 106 is coupled to the capacitor 108 and to the VCO 110.
At start-up of the PLL (not shown), the start-up signal 104 is generated by the external source and transmitted to the switch 106 where it causes the switch 106 to a go to a conducting state. Then, a voltage signal generated by the voltage source 102 is transmitted to the VCO 110 by way of the switch 106. The VCO 110 generates an output signal based on the magnitude of the voltage signal. The frequency of the output signal depends on the magnitude of the voltage signal.
The start-up circuit 100 is switched to an OFF state after a predetermined time has elapsed. Thereafter, the PLL (not shown) begins its frequency and phase acquisition of the output signal based on a reference signal. The PLL compares the frequency of the reference signal and the output signal to generate a control voltage. The control voltage is transmitted to the VCO 110. Thereafter, the VCO 110 varies the frequency and the phase of the output signal based on the control voltage.
The start-up circuit 100 is switched to an ON state for a predetermined time by the start-up signal 104. The magnitude of the voltage signal generated by the voltage source 102 is constant. The VCO 110 generates an output signal based on the magnitude of the voltage signal generated by the voltage source 102, and the predetermined time for which the start-up circuit is in the ON state. Thus, the frequency attained by the output signal depends on the magnitude of the voltage signal and the predetermined time for which the start-up signal is in ON state. After switching the start-up circuit 100 to an OFF state, the PLL starts its operation of frequency and phase acquisition of the output signal based on the reference signal. The time required by the PLL to attain the frequency and phase of the output signal depends on the frequency of the output signal just before switching the start-up circuit 100 to an OFF state. Further, the frequency attained by the output signal, during the operation of the start-up circuit 100, depends on the predetermined time and the magnitude of the voltage signal generated by the voltage source 102. Thus, the time required by the PLL for frequency and phase acquisition of the output signal depends on the predetermined time for which the start-up circuit was in the ON state and the magnitude of the voltage signal generated by the voltage source 102. This leads to uncertainty concerning the response time of the PLL.
It would be advantageous to have a start-up circuit for a PLL that turns off with more certainty and more quickly either when or near to when a lock is acquired.